The present invention relates broadly to a power on reset circuit, and in particular to a ratioed power on reset apparatus.
Typically prior art power on reset (POR) circuits employed discrete components to establish RC time constants to establish and control the power on reset (POR) pulse. This technique presents problems and difficulties in maintaining a POR signal for power supplies, V.sub.DD with slow rise times which exceed the RC time constant established by the POR circuit. Also many POR circuits result in a undesirable quiescent current. The present invention provides a circuit that relies on voltage levels rather than voltage transients to establish a POR signal and ends in a zero current state.
The state of the art of power on reset circuits is well represented and alleviated to some degree by the prior art apparatus and approaches which are contained in the following U.S. patents and incorporated by reference herein:
U.S. Pat. No. 4,553,054 issued to Kase et al on Nov. 12, 1985; PA0 U.S. Pat. No. 3,895,239 issued to Alaspa on July 15, 1975; PA0 U.S. Pat. No. 4,385,245 issued to Ulmer on May 24, 1983; PA0 U.S. Pat. No. 4,196,362 issued to Maehashi on Apr. 1, 1980; PA0 U.S. Pat. No. 3,950,654 issued to Broedner et al on Apr. 13, 1976; and PA0 U.S. Pat. No. 3,753,011 issued to Faggin on Aug. 14, 1973.
Kase et al discloses a power on reset circuit for use with a microprocessor to trigger the microprocessor's initialization subroutine. A rest pulse is applied to the microprocessor 4 when a power supply voltage V.sub.DD is applied to terminal 10. The duration of the output pulse produced by the patented circuit is not affected by the rise time of the applied voltage V.sub.DD, the pulse duration being determined by the ratio of the capacities of the capacitors 16 and 18.
Alaspa discloses an automatic power on reset circuit which is adapted for use on complementary MOS integrated circuit semiconductor dies. The circuit includes a voltage reference stage followed by an amplifier stage. A PN diode is coupled in series with a diode-connected MOSFET and a low current MOSFET device to provide a slight overdrive to the P-channel MOSFET of a CMOS inverter, which determines the initial output level thereof. As the voltage applied to the power supply conductor increases, the switching point of the amplifier-inverter stage varies until the output thereof assumes the opposite logic level. This transition of the output of the amplifier inverter stage is applied to wave shaping circuitry and an output circuit which reliably produces the desired reset signal.
Ulmer discloses a power on reset circuit which deletes the need for resistors uses a current source transistor and a capacitor to provide a minimum time for the power on reset signal.
Machashi generates a clear signal for initializing a logic circuit when the power supply voltage reaches or exceeds a predetermined level.
Broedner et al is concerned with an initializing circuit which includes feedback and is used to initialize all the relevant storage elements in an electronic calculator.
Faggin shows a circuit for setting a flip-flop using MOS technology and not requiring the fabrication of an RC circuit. The present invention is directed to a ratioed power on reset circuit that addresses the short comings of the prior art apparatus.